Synopsys Design Compiler Tutorial 2021

With low-power designs ubiquitous, DC 2021 introduces set_voltage for multiple power domains.

create_voltage_domain -name VDD_CORE -voltage 0.8
create_voltage_domain -name VDD_IO -voltage 1.8
set_voltage 0.8 -domain VDD_CORE
set_voltage 1.8 -domain VDD_IO
set_level_shifter_strategy -domain VDD_CORE -from_domain VDD_CORE -to_domain VDD_IO INSERT_LEVEL_SHIFTERS

Below is a template you can use to run synthesis in batch mode.

# run_dc.tcl
# 1. Setup
source .synopsys_dc.setup
# 2. Define Design Library
define_design_lib WORK -path ./WORK
# 3. Read Design
analyze -format verilog [glob ./rtl/*.v]
elaborate top_module
current_design top_module
link
check_design
# 4. Constraints
create_clock -name clk -period 5 [get_ports clk]
set_input_delay -max 1 -clock clk [all_inputs]
set_output_delay -max 1 -clock clk [all_outputs]
set_load 0.1 [all_outputs]
set_max_area 0
# 5. Compile
compile_ultra
# 6. Reports
redirect -tee ./reports/timing.rep  report_timing 
redirect -tee ./reports/area.rep  report_area -hierarchy 
redirect -tee ./reports/power.rep  report_power
# 7. Outputs
change_names -rules verilog -hierarchy
write -format verilog -hierarchy -output ./outputs/top_netlist.v
write_sdc ./outputs/top.sdc
exit

Fix: Use set_driving_cell on all input ports. DC 2021 is stricter about floating inputs. synopsys design compiler tutorial 2021

The new report_eco_sequence command logs every change made during incremental synthesis, allowing for transparent late-stage modifications without breaking functional equivalence.

Once the design meets timing constraints, you need to write out the results for the Place & Route (P&R) team. Below is a template you can use to

create_clock -name clk -period 10.0 [get_ports clk]

Open a terminal and invoke the GUI or shell mode. Fix: Use set_driving_cell on all input ports

dc_shell -gui

Pro tip for 2021: Use dc_shell -64bit -legacy_ui if you prefer the classic Tcl prompt over the new Python-driven interface.

| Action | Command | |--------|---------| | Check design | check_design | | Show clock | report_clock | | Reset design | remove_design -all | | Change naming rule | define_name_rules ... | | Ungroup hierarchies | ungroup -flatten -all | | Set max area | set_max_area 0 | | Set max fanout | set_max_fanout 20 [current_design] |